I prefer Verilog but what you say is true or at least should be true if you want... | Hacker News

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blackguardx on June 19, 2015 | parent | context | favorite | on: Designing a CPU in VHDL, Part 1: Rationale, Tools,...

I prefer Verilog but what you say is true or at least should be true if you want to end up with a good, easily debuggable result.

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